Design of a DC/DC-controller-adaptable test and trim circuit

A DC/DC-controller-adaptable test and trim circuit is designed based on the commercial process of 0.25μm BCD. Based on the thought of pin multiplexed and by applying specific signals on specific pins of the circuit, it could readout internal signals, trim key parameters, and overcome parasitic effects of package on high voltage resolution and large current applications without effecting the common pin signals’ status in normal operation, featuring easy test operation, cheap test cost and extensive test range. As a result, the size problem that traditional PAD probe trim need to occupy more area when trimming more fuses would be relieved, the cost problem that traditional laser trim need expensive equipment and programs would be avoided, and the common problem that both PAD probe trim and laser trim can only be feasible at wafer level and unfit to be used in high voltage resolution and large current application would be improved. The circuit is comprised of register clock and data input circuit, test and trim enable circuit, test and trim array circuit, and test data output circuit. Simulation results show that under the circumstance of open loop, by configuring specific data bits, the design lends itself well to test internal signals such as oscillator’s output and parameters such as on-resistance, and trim critical parameters such as reference voltage etc.