A high reliability, multi-bit parallel readout in-memory computing scheme based on STT-MRAM

In-memory computing technology is one of the most effective ways to solve the bottleneck of traditional von Neumann computing architecture. Although STT-MRAM has the advantages of non-volatile, low power consumption and high durability, its small sensing margin poses a challenge to the read reliability of sensitive amplifier (SA) design. Although the in-memory computing scheme based on two transistors and two magnetic tunnel junction (2T2MTJ) cells can effectively improve the read sensing margin and bit operation accuracy, the area of the memory array increases exponentially. For 1T1MTJ unit, we proposed a high reliability, multi-bit parallel readout in-memory computing scheme using an enhanced multi-bit current-sensitive amplifier (MBCSA) for branch current calculation and three independent reference units. The simulation results indicates that, when compared with the 1T1MTJ and 2T2MTJ schemes with precharge current-sensitive amplifier, the proposed scheme can improve the accuracy rates of the bitwise in-memory computing by 4.07% and 1.65%, respectively, in the typical case, and further enhance the read accuracy and robustness when with a small TMR and a low V_DD. Moreover, the proposed scheme can simultaneously perform "AND" and "OR" bitwise logical operations for two pairs of data units in a 6 ns read cycle as well as the results of "NAND" and "NOR" and output four kinds of bit logic operation results.