Research on reading acceleration technology of embedded flash

Embedded Flash has increasingly become an important program and data memory in microcontroller due to its advantages in cost and storage density. However, the relatively slow read speed of embedded Flash restricts the overall performance of the microcontroller, so it is very important to improve the read performance of instruction and data in Flash. In order to improve the read performance of the embedded Flash in the microcontroller, a Flash controller based on cache and prefetch is proposed, and the current cache and prefetch are optimized. in view of the problem of poor adaptability of the existing cache, a cache line size adaptive technology is proposed for optimization. Aiming at the problem of high missing cost and high power consumption when accessing the set-associative cache in the traditional way, a way hit prediction technology is proposed for optimization. Aiming at the problem of low accuracy of the existing prefetching technology, a stride prefetching technology is proposed for optimization. Finally, an embedded Flash controller was designed and implemented, and integrated into the SoC system, and a verification platform was built for functional simulation and FPGA verification. Experimental results show that after adopting the cache line size adaptive technology, the performance of the processor to read embedded Flash is significantly improved (103%); after adopting the way hit prediction technology, the performance of the processor to read embedded Flash is further improved (2%). After adopting stride prefetching technology, the performance of DMA reading embedded Flash has been significantly improved (50%).