HE Wen, ZHU Yongxin, WANG Hui, HUANG Zunkai. Accelerator design and implementation for automatic searching neural network[J]. Microelectronics & Computer, 2021, 38(11): 88-94. DOI: 10.19304/J.ISSN1000-7180.2021.0279
Citation: HE Wen, ZHU Yongxin, WANG Hui, HUANG Zunkai. Accelerator design and implementation for automatic searching neural network[J]. Microelectronics & Computer, 2021, 38(11): 88-94. DOI: 10.19304/J.ISSN1000-7180.2021.0279

Accelerator design and implementation for automatic searching neural network

  • In recent years, the Automatic Searching Neural Networks obtained through Neural Architecture Search (NAS) has performed quite prominently in visual tasks, but their complex and variable convolution scale and convolution types limit their application in edge-side devices. To solve this problem, a high flexibility and high frame rate accelerator is proposed to accelerate automatic searching neural networks represented by MnasNet. Firstly, the Array Multiplexing Mixed Convolution(AMMC) structure is proposed for its rich convolution types, which can realize the parallel processing of different convolutions in different directions without using additional MAC resources. Secondly, a variable precision Configurable Multiple Selection Activation(CMA) structure is proposed, which can effectively realize the high-precision fitting of various activation functions. When the accelerator is deployed on the zcu102 chip of Xilinx with a 32*32 MAC scale, the clock frequency can reach 200 MHz, the power consumption of the accelerator is 3.2 w, and the actual operating frame rate for 224×224 size image of MnasNet-a1 is 272.9 fps.
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