A parallel input re-encoding circuit to reduce 3-D VRRAM thermal crosstalk effects

3-D Vertical Resistive Random Access Memory (VRRAM) is a new architecture widely studied to reduce the cost of resistive random access memory cells. The current performance evaluation of 3-D VRRAM arrays mainly focuses on the analysis of write and read margins. However, the thermal crosstalk effect in 3-D VRRAM is also a problem worthy of attention. Excessive thermal crosstalk will significantly reduce the reliability of memory cells in the array. This paper proposes a parallel write re-encoding circuit to reduce the thermal crosstalk effect caused by massive parallel writes by re-encoding the input data. The experimental results show that when the parallel write array size is 4×4, 4×8, and 8×8, the input re-encoding circuit proposed in this paper can reduce the thermal crosstalk effect by 21.8%, 23.9%, and 12.2%, respectively. Besides, using the write re-encoding proposed in this paper will only increase the write latency by 3% and the additional area of 0.07%.