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一种针对QCA电路的门级布局布线算法设计

邝锐 彭斐 张永强 解光军

邝锐, 彭斐, 张永强, 解光军. 一种针对QCA电路的门级布局布线算法设计[J]. 微电子学与计算机, 2021, 38(9): 79-83.
引用本文: 邝锐, 彭斐, 张永强, 解光军. 一种针对QCA电路的门级布局布线算法设计[J]. 微电子学与计算机, 2021, 38(9): 79-83.
KUANG Rui, PENG Fei, ZHANG Yongqiang, XIE Guangjun. A gate-level placement and routing algorithm design for QCA circuits[J]. Microelectronics & Computer, 2021, 38(9): 79-83.
Citation: KUANG Rui, PENG Fei, ZHANG Yongqiang, XIE Guangjun. A gate-level placement and routing algorithm design for QCA circuits[J]. Microelectronics & Computer, 2021, 38(9): 79-83.

一种针对QCA电路的门级布局布线算法设计

基金项目: 

中央高校基本科研业务费专项资金 JZ2020HGQA0162

中央高校基本科研业务费专项资金 JZ2020HGTA0085

详细信息
    作者简介:

    邝锐  男,(1994-),硕士研究生.研究方向为量子电路设计及算法开发

    彭斐  男,(1985-),博士研究生. 研究方向为量子电路自动化设计工具开发和算法设计

    张永强  男,(1991-),博士,讲师,硕士生导师.研究方向为微纳电路与系统、随机计算

    通讯作者:

    解光军(通讯作者)  男,(1970-),博士,教授,博士生导师.研究方向为微纳电路与系统、集成电路设计.E-mail:gjxie8005@hfut.edu.cn

  • 中图分类号: TP391.9

A gate-level placement and routing algorithm design for QCA circuits

  • 摘要: 量子点元胞自动机(QCA)被认为是克服传统CMOS局限性的一种极有前景的解决方案.近年来,QCA电路的自动化设计工具的开发越来越受到研究者的关注,布局和布线算法则是其中至关重要的一环.算法设计的关键问题是时钟方案和时钟同步性约束.本文提出了一种门级布局和布线算法,在时钟方案约束的布局区域内预先计算和缓存路径信息,并应用深度优先搜索策略搜索正确的电路布局布线结果.该算法采用C ++编程语言实现,仿真结果验证了算法的正确性.
  • 图  1  算法框架图

    图  2  路径计算示意图

    图  3  C17电路布局布线图

    表  1  仿真结果

    circuit this work Ropper[10]
    area pr time total time area pr time total time
    C17 72 0.95 ms 2.92 s 80 275.53 ms 16.83 s
    Mux21 35 0.17 ms 2.67 s 30 153.83 ms 16.34 s
    1bitadder 16 0.11 ms 2.683 s 16 275.53 ms 16.36 s
    下载: 导出CSV
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出版历程
  • 收稿日期:  2020-12-03
  • 修回日期:  2021-01-11
  • 刊出日期:  2021-09-05

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