李飞.一种适用于DC/DC控制器的测试及修调电路设计[J]. 微电子学与计算机,2023,40(3):107-116. doi: 10.19304/J.ISSN1000-7180.2022.0381
引用本文: 李飞.一种适用于DC/DC控制器的测试及修调电路设计[J]. 微电子学与计算机,2023,40(3):107-116. doi: 10.19304/J.ISSN1000-7180.2022.0381
LI F. Design of a DC/DC-controller-adaptable test and trim circuit[J]. Microelectronics & Computer,2023,40(3):107-116. doi: 10.19304/J.ISSN1000-7180.2022.0381
Citation: LI F. Design of a DC/DC-controller-adaptable test and trim circuit[J]. Microelectronics & Computer,2023,40(3):107-116. doi: 10.19304/J.ISSN1000-7180.2022.0381

一种适用于DC/DC控制器的测试及修调电路设计

Design of a DC/DC-controller-adaptable test and trim circuit

  • 摘要: 采用0.25 μm BCD商用工艺,设计了一种适用于DC/DC控制器的测试及修调电路. 该电路基于引脚功能复用的思路,通过对特定引脚施加特定信号,在不影响控制器正常工作时的引脚信号状态的情况下,既能够在圆片级或封装后实现内部信号的读取以及参数指标的修调,又能够克服封装寄生效应对高电压精度以及大电流测试的影响,具有测试操作简单、测试成本低廉、测试范围广泛等优点. 该电路缓解了传统PAD扎针加压方案在熔丝数量较多时突出的面积问题;解决了传统激光切割方案需要昂贵激光修调设备及编写ATE程序的成本问题;改善了两种传统修调方案均只能在圆片级测试,不适合高精度、大电流测试的应用问题. 该电路内部结构包括寄存器时钟及数据输入电路、测试及修调使能电路、测试及修调阵列电路、测试数据输出电路. 仿真结果表明,在DC/DC控制器开环状态下,通过配置特定端口的数据位,能够通过测试电路实现振荡器输出振荡信号等内部典型信号的输出,实现关键指标导通电阻的测试,通过修调电路实现关键参数基准电压精度的修调.

     

    Abstract: A DC/DC-controller-adaptable test and trim circuit is designed based on the commercial process of 0.25μm BCD. Based on the thought of pin multiplexed and by applying specific signals on specific pins of the circuit, it could readout internal signals, trim key parameters, and overcome parasitic effects of package on high voltage resolution and large current applications without effecting the common pin signals’ status in normal operation, featuring easy test operation, cheap test cost and extensive test range. As a result, the size problem that traditional PAD probe trim need to occupy more area when trimming more fuses would be relieved, the cost problem that traditional laser trim need expensive equipment and programs would be avoided, and the common problem that both PAD probe trim and laser trim can only be feasible at wafer level and unfit to be used in high voltage resolution and large current application would be improved. The circuit is comprised of register clock and data input circuit, test and trim enable circuit, test and trim array circuit, and test data output circuit. Simulation results show that under the circumstance of open loop, by configuring specific data bits, the design lends itself well to test internal signals such as oscillator’s output and parameters such as on-resistance, and trim critical parameters such as reference voltage etc.

     

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