曹正州, 刘国柱, 单悦尔, 沈广振, 涂波, 徐玉婷. 一款用于Flash型FPGA的配置电路设计[J]. 微电子学与计算机, 2022, 39(11): 118-128. DOI: 10.19304/J.ISSN1000-7180.2022.0285
引用本文: 曹正州, 刘国柱, 单悦尔, 沈广振, 涂波, 徐玉婷. 一款用于Flash型FPGA的配置电路设计[J]. 微电子学与计算机, 2022, 39(11): 118-128. DOI: 10.19304/J.ISSN1000-7180.2022.0285
CAO Zhengzhou, LIU Guozhu, SHAN Yueer, SHEN Guangzhen, TU Bo, XU Yuting. A configuration circuit design for Flash-based FPGA[J]. Microelectronics & Computer, 2022, 39(11): 118-128. DOI: 10.19304/J.ISSN1000-7180.2022.0285
Citation: CAO Zhengzhou, LIU Guozhu, SHAN Yueer, SHEN Guangzhen, TU Bo, XU Yuting. A configuration circuit design for Flash-based FPGA[J]. Microelectronics & Computer, 2022, 39(11): 118-128. DOI: 10.19304/J.ISSN1000-7180.2022.0285

一款用于Flash型FPGA的配置电路设计

A configuration circuit design for Flash-based FPGA

  • 摘要: 为了能够为flash型FPGA中的flash开关单元提供稳定的擦除、编程和读取操作电压,基于0.11 μm 2P8M flash工艺,设计了一款用于flash型FPGA的配置电路.根据flash cell的操作条件和flash型FPGA的特点设计了层次化的字线电路、带校验功能的位线电路、低纹波的电荷泵电路、多级的电平转换电路、灵活的衬底电压电路以及配置控制电路.该配置电路是执行配置算法流程的基础,为flash型FPGA配置过程中的flash cell提供了高精度和稳定的操作电压,保证了flash cell在擦除和编程后的阈值电压分布的一致性, 使flash型FPGA的性能得以充分发挥.仿真结果表明:擦除时字线的驱动能力为1.2 mA,输出电压-10.5 V,误差小于±0.1 V,建立时间为11.2 μS; 位线驱动能力为1.2 mA,输出电压8.8 V,误差小于±0.1 V,建立时间为7.5 μS。编程时字线的驱动能力为1.2 mA,输出电压9.8 V,误差小于±0.1 V,建立时间为2.3 μS; 位线驱动能力为4.4 mA,输出电压-8.0 V,误差小于±0.1 V,建立时间为2.5 μS.设计满足了flash cell的操作条件,最终实现对350万门flash型FPGA共26 836 992 bits(2 912 bl*9 216 wl)码流的配置.

     

    Abstract: In order to provide a stable erasing, programming and reading operating voltage for flash switch unit in flash-based FPGA, a configuration circuit for flash-based FPGA was designed based on 0.11 μm 2P8M flash process. According to the operating conditions of flash cell and the characteristics of flash-based FPGA, the configuration circuit is designed with hierarchical word line circuit, bit line circuit with check function, low ripple charge pump circuit, multi-level level conversion circuit, flexible substrate voltage circuit and configuration control circuit, which is the basis of the implementation of the configuration algorithm flow. It provides high precision and stable operating voltage for flash cell in the process of flash-based FPGA configuration, ensures the consistency of threshold voltage distribution of flash cell after erasure and programming, and gives full play to the performance of flash-based FPGA. The simulation results show that the driving capacity of the word line is 1.2 mA, the output voltage is -10.5 V, the error is less than ±0.1 V, and the establishment time is 11.2 μS. The bit line drive capacity is 1.2 mA, the output voltage is 8.8 V, the error is less than ±0.1 V, and the establishment time is 7.5 μS. In programming, the driving capacity of the word line is 1.2 mA, the output voltage is 9.8V, the error is less than ±0.1 V, and the establishment time is 2.1 μS. The bit line drive capacity is 4.4 mA, the output voltage is -8.0 V, the error is less than ±0.1 V, and the establishment time is 2.3 μS. The design meets the operating conditions of Flash cell, and finally realizes the configuration of 3.5 million flash-based FPGA with 26 836 992 bits (2 912 BL * 9 216 WL) bit streams.

     

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