Abstract: This paper introduces a special digital signal processor (DSP) in SerDes receiver based on 4-pulse amplitude modulation (pam4). It is mainly committed to solving the data recovery problem in a high-speed serial interface under the ultra-high transmission rate of 50~64gb/s and 20-30db large channel attenuation. The 32 channels parallel structure of this DSP enables the system to process 50~64gb/s high-speed data signals; At the same time, 16 tap feedforward equalizer (FFE) is applied to solve the problem of data recovery under 20~30db large channel attenuation; The adaptive algorithm using the least mean square algorithm (LMS) is combined with FFE, so that it can adaptively find the best high-frequency compensation under different channel attenuation and eliminate the attenuation effect and inter symbol interference (ISI) caused by the transmission channel; At the same time, in order to solve the timing tension of the feedback loop caused by the parallel structure of the traditional decision feedback equalizer (DFE), a DFE with improved pre-decision structure is adopted, which is cascaded after the FFE to eliminate the remaining ISI and determine the correct data signal, so as to cooperate with the FFE to balance and recover the original data signal. This DSP architecture was manufactured by using 28nm CMOS process after simulation verification. Simulation and test verification found that it can achieve a good equalization effect at 50gb/s transmission rate and 20~30db channel attenuation. The final DSP chip area is 2.02 mm², and the bit error rate is as low as 5.21e-9.