施隆照, 郭冀闽. 基于802.11ac的FFT/IFFT处理器设计[J]. 微电子学与计算机, 2016, 33(3): 95-98.
引用本文: 施隆照, 郭冀闽. 基于802.11ac的FFT/IFFT处理器设计[J]. 微电子学与计算机, 2016, 33(3): 95-98.
SHI Long-zhao, GUO Ji-min. Design of an FFT/IFFT Processor for 802.11ac System[J]. Microelectronics & Computer, 2016, 33(3): 95-98.
Citation: SHI Long-zhao, GUO Ji-min. Design of an FFT/IFFT Processor for 802.11ac System[J]. Microelectronics & Computer, 2016, 33(3): 95-98.

基于802.11ac的FFT/IFFT处理器设计

Design of an FFT/IFFT Processor for 802.11ac System

  • 摘要: 针对IEEE 802.11ac MIMO-OFDM系统设计了一种8通道128点FFT/IFFT处理器, 该处理器采用MRMDC结构, 支持8通道数据的并行处理, 有效降低了硬件复杂度和提高了数据吞吐率.提出的数据输入和输出顺序调整结构, 可以实现数据自然顺序的输入和输出, 从而实现了和MIMO-OFDM系统中的其他模块直接进行数据传递.FFT/IFFT处理器由Verilog语言实现, 并用Synopsys公司的Design Compiler在SMIC 0.18 μm CMOS工艺库下进行逻辑综合, 内部数据和旋转因子的宽度采用12 bit, 最高工作频率可达100 MHz, 数据吞吐率可达1 Gb/s.

     

    Abstract: In this paper, an area-efficient 8-channel 128 point MRMDC FFT/IFFT processor is proposed for IEEE 802.11ac standard MIMO-OFDM system.The proposed FFT processor is based on MRMDC architecture and supports 8 spatial data steams. Using input and output data sequential reorder architecture in the proposed FFT processor can realize eight input and output spatial data streams all in natural order, and can be used directly in MIMO-OFDM system.The proposed FFT processor is designed in hardware description language (HDL) and synthesized to gate-level circuit using SMIC 0.18μm CMOS process.We choose 12-bit word width for the internal data path and twiddle factors.The processor can provide a thoughput rate of up to 1 Gb/s and maximal clock rate of 100 MHz.

     

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