Abstract: Based on IBM SOI-0.18 μm CMOS process, a high PAE Class-E power amplifier is proposed. This power amplifier is composed of two stages. A negative capacitance is used at output stage in order to offset parasitic capacitance and improve efficiency. The common-gate transistor of output stage adopts self-biased technique which prevents the transistor from being broken down. Driver stage consists of Class-E, which turns the transistor of output stage on and off more efficiently. The network is used to improve overlap of current and voltage of output stage. By employing these techniques, the power amplifier can deliver 23.44 dBm output power at 2.4 GHz with 58.99% power added efficiency at 2.8-v supply.