余振波, 聂言硕, 宋宇鲲, 侯宁. 一种自适应可重构通用浮点加速器的设计[J]. 微电子学与计算机, 2021, 38(1): 89-94.
引用本文: 余振波, 聂言硕, 宋宇鲲, 侯宁. 一种自适应可重构通用浮点加速器的设计[J]. 微电子学与计算机, 2021, 38(1): 89-94.
YU Zhen-bo, NIE Yan-shuo, SONG Yu-kun, HOU Ning. Design of an adaptive reconfigurable general-purpose floating-point accelerator[J]. Microelectronics & Computer, 2021, 38(1): 89-94.
Citation: YU Zhen-bo, NIE Yan-shuo, SONG Yu-kun, HOU Ning. Design of an adaptive reconfigurable general-purpose floating-point accelerator[J]. Microelectronics & Computer, 2021, 38(1): 89-94.

一种自适应可重构通用浮点加速器的设计

Design of an adaptive reconfigurable general-purpose floating-point accelerator

  • 摘要: 用加速器因其专业性过强往往缺乏一定的灵活性,在处理不同类型的应用时不可避免的导致能效比的下降.本文设计了一款自适应可重构浮点加速器,它可以根据计算任务需求和可重构计算资源使用情况,在运行时将计算任务映射到可重构计算资源,具有自适应可重构的能力.该浮点加速器整体采用“RISC-V+可重构浮点运算单元”的架构,可重构浮点运算单元由一系列粗粒度浮点运算器构成,负责具体的浮点计算.该设计在Xilinx Ultrascale XCVU440FPGA芯片上进行了原型验证,结果表明,该浮点加速器具有较广的应用面,运算效率高,算法适应性强.

     

    Abstract: Application-specific accelerators often lack flexibility due to their professionalism, which inevitably leads to the decrease ofenergy efficiency during the execution of a wide range of applications. In this paper, an adaptive reconfigurable floating-point accelerator is designed, which can automatically map computing tasks to reconfigurable computing resources at runtime basing on computing task requirements and the status of reconfigurable computing resources. The floating-point accelerator uses the architecture of "RISC-V + Reconfigurable Floating-point Arithmetic Unit". The reconfigurable floating-point arithmetic unit consists of a series of coarse-grained floating-point arithmetic units, which are responsible for specific floating-point calculations.The design has been prototypical verified on the Xilinx Ultrascale XCVU440 FPGA chip, and the results show that the floating-point accelerator has wider applicability, high operation efficiency, and high algorithm adaptability.

     

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